1. Field of the Invention
The present invention generally relates to electrostatic discharge protection techniques for semiconductor integrated circuitry, and, more specifically, relates to an electrostatic discharge protection circuit triggered at a low voltage.
2. Description of the Prior Art
Electrostatic discharge, ESD hereinafter, is a common phenomenon that occurs during handling of semiconductor integrated circuit ("IC") devices. Electrostatic charges may accumulate and cause potentially destructive effects on an IC device. ESD stressing typically can occur during a testing phase of IC fabrication, during installation of the IC onto a circuit board, as well as during use of equipment into which the IC has been installed. Damage to a single IC due to poor ESD protection in an electronic device can partially or sometimes completely hamper its operation.
Sub-micron CMOS ICs have become increasingly vulnerable to ESD damage due to advanced processes, such as the use of a lightly-doped drain ("LDD") structure and clad silicide diffusions. Therefore, lateral silicon-controlled rectifiers (LSCRs) have been proposed, for example, in U.S. Pat. No. 5,012,317, as ESD protection circuits for facilitating ESD protection. The cross-sectional view of a conventional lateral silicon-controlled rectifier fabricated onto a semiconductor substrate is illustrated in FIG. 1.
As shown in FIG. 1, the silicon-controlled rectifier is fabricated on a P-type silicon substrate 10 in which an N-well region 11 is formed. A pair of a P-type doped region 12 and an N-type doped region 13 are formed within the extent of the N-well region 11 and spaced apart from each other, while another pair of an N-type doped region 14 and a P-type doped region 15 are formed within the extent of the P-type silicon substrate 10 and spaced apart from each other. The P-type doped region 12 and the N-type doped region 13 are connected together to an IC pad 1. The IC pad 1 is electrically connected to an internal circuit 2, which is vulnerable to ESD damage and should be protected by the lateral silicon-controlled rectifier. In addition, the N-type doped region 14 and the P-type doped region 15 are connected together to a potential node V.sub.SS, which is generally connected to ground under normal operation.
Accordingly, the P-type doped region 12, the N-well region 11, and the P-type silicon substrate 10 serve as the emitter, base, collector, respectively, of a PNP bipolar junction transistor 20, while the N-well region 11, the P-type silicon substrate 10, and the N-type doped region 14 serve as the collector, base, emitter, respectively, of an NPN bipolar junction transistor 21. Referring to FIG. 2, the equivalent circuit diagram of the conventional lateral silicon-controlled rectifier shown in FIG. 1 is schematically depicted. Furthermore, as shown in FIG. 2, resistors 22 and 23 stand for the respective spreading resistance of the N-well region 11 and the P-type silicon substrate 10.
When ESD occurs at the IC pad 1, the P/N junction between the N-well region 11 and the P-type silicon substrate 10 breaks down and then forward biases the P/N junction between the P-type silicon substrate 10 and the N-type doped region 14. Therefore, the lateral silicon-controlled rectifier composed of the PNP transistor 20 and NPN transistor 21 is triggered to conduct the resulting ESD current and thus bypass the ESD stress so as to protect the internal circuit 2 from ESD damage.
As mentioned above, triggering of the conventional lateral silicon-controlled rectifier to turn on and thus bypass the ESD stress heavily relies on the junction breakdown between the N-well region 11 and the P-type silicon substrate 10. However, both N-well region 11 and the P-type silicon substrate 10 have doping concentrations so low that the trigger voltage of the lateral silicon-controlled rectifier is roughly 30V or more. For example, with CMOS fabrication technology of 0.6.about.0.8 .mu.m, gate oxides of about 150.about.200 .ANG. in thickness, utilized in the internal circuit 2, may be damaged at voltages lower than the trigger voltage of the conventional lateral silicon-controlled rectifier.
To lower the trigger voltage, U.S. Pat. No. 5,465,189 has proposed "A LOW VOLTAGE TRIGGERING SEMICONDUCTOR CONTROLLED RECTIFIER" as illustrated in FIG. 3. In addition to those elements disclosed in FIG. 1, another N-type doped region 16 and a gate structure 17 are involved in this conventional ESD protection circuit. The N-type doped region 16 is provided with one portion formed in N-type well region 11 and another portion formed in the P-type silicon substrate 10. In other words, the N-type doped region 16 stretches across the junction of the N-well region 11 and the P-type silicon substrate 10. The gate structure 17, which is provided with a gate dielectric layer 18 and a gate electrode 19 connected to the V.sub.SS node, is formed to cover a portion of silicon substrate 10 between the N-type doped regions 14 and 16.
FIG. 4 is the equivalent circuit of FIG. 3. In FIG. 4, reference numeral 24 stands for an metal-oxide-semiconductor field-effect transistor (MOSFET) constituted by the N-type doped regions 14 and 16, the portion of the silicon substrate 10 between the N-type doped regions 14 and 16, and the gate structure 17. When ESD occurs at the IC pad 1, the MOS transistor 24 enters breaks down, thereby triggering the lateral silicon-controlled rectifier to conduct a discharge current. Accordingly, the trigger voltage of the ESD protection circuit as shown in FIG. 3 can be lowered to the breakdown voltage of the MOS transistor 24.
However, the MOS transistor 24 can not be integral with an output buffer when the IC pad 1 denotes an output pad. Moreover, as integrated circuit processing advances to smaller dimensions the resistance of the substrate decreases, making it harder to ESD trigger the lateral silicon-controlled rectifier.
For the foregoing reason, there is a need for an ESD protection circuit, which can be triggered at a decreased voltage, particularly adaptable for CMOS circuits with low resistance substrates.